This invention relates to an execution rate controlling device for controlling an execution rate of central processing unit.
The central processing unit carries out a processing operation in synchronism with a first clock signal supplied from a first clock oscillator. The central processor unit has an operation rate decided by the first clock oscillator. The first clock oscillator is therefore used for the central processing unit.
The execution rate controlling device suspends operation of the central processing unit periodically. The execution rate is decided by the operation rate and a suspended duration of the operation. In this manner, the execution rate controlling device controls an execution rate of the central processing unit.
According to prior art, the execution rate controlling device comprises a data register, a decrement counter, and a second clock oscillator for the decrement counter. The data register holds a hold time data representative of the suspended duration that is in inverse proportion to the execution rate of the central processing unit. The second clock oscillator produces a second clock signal. The decrement counter is connected to the data register, the second clock oscillator, and the central processing unit. The decrement counter preloads a hold time data when it receives a periodical refresh signal for a DRAM of a main memory. The decrement counter counts down a count from the hold time data to zero in synchronism with the second clock signal. The decrement counter produces a hold demand signal from a time instant of count zero to another time instant of reception of the refresh signal. The central processing unit suspends operation during reception of the hold demand signal.
A reduction rate is a ratio of the execution rate to the operation rate. If the operation rate varies with the first clock oscillator, then the reduction rate varies. This is because the execution rate controlling device depends on the refresh signal and the second clock signals and is independent of the first clock oscillator. It is therefore necessary to set a new hold time data in the data register when the first clock oscillator generates the first clock signal with a different clock period.
In this manner, the execution rate controlling device controls the execution rate of the central processing unit.